// Stage 3: Execute (ALU) always @(posedge clk) begin ID_EX_instr <= IF_ID_instr; ID_EX_pc <= IF_ID_pc; ID_EX_rs1 <= reg_data1; ID_EX_rs2 <= reg_data2; end
// ALU inside execute wire [31:0] alu_out = (opcode == ADD) ? ID_EX_rs1 + ID_EX_rs2 : ...; Advanced Chip Design- Practical Examples In Verilog
Add write buffer, ECC, and bank interleaving. 4. Clock Domain Crossing (CDC) Example: 2-flop synchronizer (single-bit) module sync_single ( input clk_dst, rst_n, input sig_src, output reg sig_dst ); reg meta, sync; // Stage 3: Execute (ALU) always @(posedge clk)
assign sig_dst = sync; endmodule module async_fifo #(DEPTH=8, WIDTH=16) ( input wclk, rclk, wrst_n, rrst_n, input wr_en, rd_en, input [WIDTH-1:0] wdata, output [WIDTH-1:0] rdata, output full, empty ); reg [WIDTH-1:0] mem [0:DEPTH-1]; reg [$clog2(DEPTH):0] wptr, rptr; // Gray coded output reg sig_dst )
Gray code pointers, full/empty detection, metastability hardening. 5. Low-Power Design Techniques Clock Gating (Integrated with synthesis) module clock_gated_reg ( input clk, en, d, output reg q ); wire gated_clk; assign gated_clk = clk & en; // NOT for FPGA (glitchy) // Better: use latch-based AND gate reg en_latch; always @(clk or en) if (!clk) en_latch = en; assign gated_clk = clk & en_latch;