Clock Divider Verilog 50 Mhz 1hz -

reg clk_50mhz; reg rst_n; wire clk_1hz;

always @(posedge clk_50mhz or negedge rst_n) begin if (!rst_n) begin count <= 0; clk_1hz <= 0; end else begin if (count == HALF_CYCLE) begin count <= 0; clk_1hz <= ~clk_1hz; end else begin count <= count + 1; end end end endmodule module clock_divider #( parameter INPUT_FREQ = 50_000_000, // Hz parameter OUTPUT_FREQ = 1 // Hz ) ( input wire clk_in, input wire rst_n, output reg clk_out ); localparam MAX_COUNT = (INPUT_FREQ / OUTPUT_FREQ) / 2 - 1; // For 50 MHz to 1 Hz: MAX_COUNT = 24,999,999 clock divider verilog 50 mhz 1hz

// Test sequence initial begin $dumpfile("dump.vcd"); $dumpvars(0, tb_clock_divider); // Initialize rst_n = 0; #100; // Release reset rst_n = 1; // Run for 2 seconds (simulation time) #2_000_000_000; // 2 seconds of simulation $finish; end reg clk_50mhz; reg rst_n; wire clk_1hz; always @(posedge

// Stage 1: 50 MHz → 100 Hz (divide by 500,000) clock_divider #(50_000_000, 100) stage1 (clk_50mhz, rst_n, clk_100hz); end else begin count &lt