Maya saved the boardview file one last time. In the REV_NOTES field, she added a new line: “Hole drilled at D-17. Dielectric thickness critical. The map had the secret—you just had to believe it was there.”
Dev zoomed into C442. “Here. The little bastard. The boardview says its positive terminal is net ‘+3V3_MEM,’ and its negative is ‘GND_REF.’ That’s fine. But when I meter it, there’s zero ohms between those nets. So either the boardview is wrong, or the physical board has a solder bridge somewhere.”
The problem was a single, stubborn short. A 3.3V rail was kissing the ground plane somewhere in the dense jungle of the south-east quadrant, near the main processor’s memory bus. Every time they powered up, a tiny puff of acrid smoke rose from C442, a decoupling capacitor that wasn’t even supposed to be warm.
“Show me the boardview again,” Maya said, leaning over Dev’s monitor.
Dev stared. “You can’t overlap power and ground planes. That’s a capacitor the size of the whole board. It would oscillate like crazy.”
Dev looked at Maya. “You just diagnosed a short that didn’t exist in any netlist, any schematic, any continuity test. You diagnosed a ghost .”
“Or,” Maya said, a new thought crystallizing, “the boardview is right, and we’re misreading the layer stack-up.”
Maya grabbed a razor blade and carefully delaminated a corner of the PCB near D-17. Under the microscope, the cross-section was undeniable: inner1 and inner2 were separated by a gossamer-thin layer of fiberglass, not the standard 0.8mm. They were practically touching.
“The boardview wasn’t wrong,” Maya said, sitting back. “It was telling us the truth. We just didn’t know how to read it.”
Dev leaned in. On the boardview, the two planes showed as overlapping translucent shapes, creating a muddy brownish color. He’d always assumed that was a rendering artifact.
“ECN #442: Due to EMI issue on v3, inner2 ground plane has a cutout under U5. For v4, removed cutout. Ground and power planes now overlap in region D-17. Ensure sufficient dielectric. — L.C.”
“Overlap,” Maya whispered.
Maya saved the boardview file one last time. In the REV_NOTES field, she added a new line: “Hole drilled at D-17. Dielectric thickness critical. The map had the secret—you just had to believe it was there.”
Dev zoomed into C442. “Here. The little bastard. The boardview says its positive terminal is net ‘+3V3_MEM,’ and its negative is ‘GND_REF.’ That’s fine. But when I meter it, there’s zero ohms between those nets. So either the boardview is wrong, or the physical board has a solder bridge somewhere.”
The problem was a single, stubborn short. A 3.3V rail was kissing the ground plane somewhere in the dense jungle of the south-east quadrant, near the main processor’s memory bus. Every time they powered up, a tiny puff of acrid smoke rose from C442, a decoupling capacitor that wasn’t even supposed to be warm.
“Show me the boardview again,” Maya said, leaning over Dev’s monitor. nb8511-pcb-mb-v4 boardview
Dev stared. “You can’t overlap power and ground planes. That’s a capacitor the size of the whole board. It would oscillate like crazy.”
Dev looked at Maya. “You just diagnosed a short that didn’t exist in any netlist, any schematic, any continuity test. You diagnosed a ghost .”
“Or,” Maya said, a new thought crystallizing, “the boardview is right, and we’re misreading the layer stack-up.” Maya saved the boardview file one last time
Maya grabbed a razor blade and carefully delaminated a corner of the PCB near D-17. Under the microscope, the cross-section was undeniable: inner1 and inner2 were separated by a gossamer-thin layer of fiberglass, not the standard 0.8mm. They were practically touching.
“The boardview wasn’t wrong,” Maya said, sitting back. “It was telling us the truth. We just didn’t know how to read it.”
Dev leaned in. On the boardview, the two planes showed as overlapping translucent shapes, creating a muddy brownish color. He’d always assumed that was a rendering artifact. The map had the secret—you just had to
“ECN #442: Due to EMI issue on v3, inner2 ground plane has a cutout under U5. For v4, removed cutout. Ground and power planes now overlap in region D-17. Ensure sufficient dielectric. — L.C.”
“Overlap,” Maya whispered.